A display panel (e.g., a liquid crystal display (LCD) panel) is typically formed from an array of pixel elements (e.g., liquid crystal capacitors) arranged in rows and columns. Each row of pixel elements is coupled to a respective gate line, and each column of pixel elements is coupled to a respective source line. More specifically, each pixel element in the array is coupled to a particular gate line and source line via an “access” transistor (e.g., an n-channel metal oxide semiconductor (NMOS) transistor). For example, the gate of the transistor may be coupled to the gate line and the drain (or source) of the transistor may be coupled to the source line. Thus, the pixel element may be accessed by driving a relatively high voltage (VGH) on the gate line, which effectively turns on the access transistor. With the access transistor turned on, the liquid crystal capacitor can be updated with new pixel data by driving a voltage on the corresponding source line (e.g., the voltage level may depend on the desired color and/or intensity of the pixel value).
Each row of pixel elements is coupled to a gate driver and each column of pixel elements is coupled to a source driver. The source driver is configured to drive pixel data, via the source lines, onto the pixel elements of the array. The gate driver is configured to select a particular row of pixel elements to receive the pixel data, for example, by driving the gate line coupled to the selected row. A display panel is typically updated by successively “scanning” the rows of pixel elements (e.g., one row at a time), until each row of pixel elements has been updated. For example, the gate driver may include a shift register configured to drive each of the gate lines, in succession, based on a periodic clock signal.
In conventional gate driver implementations, the output from each stage of the shift register controls the activation (or deactivation) of a particular gate line in the array. Because each gate line is driven by a different shift register stage, the footprint of a display panel may increase significantly based on the number of pixels (or rows of pixels) in the array. Furthermore, the speed at which the shift register is able to “scan” through the array may be limited by the time required to drive each row of pixel elements with a sufficiently high gate voltage (VGH). Thus, it may be desirable to reduce the footprint of the gate driver circuitry while also increasing the speed (and flexibility) with which scans may be performed.